Design Summary: "run_benchmark"

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Full run_benchmark Metrics

- units import_verilog0 syn0 floorplan0 place0 cts0 route0 write_gds0 write_data0
errors 0 0 0 0 0 0 0 0
warnings 111 119 41 42 40 41 0 40
drvs --- --- --- 12 12 128 --- 307
drcs --- --- --- --- --- 0 --- ---
unconstrained --- --- 1670 1670 1670 1670 --- 1670
cellarea um^2 --- 1305.129 1279.920 1347.940 1347.940 1347.940 --- 1347.940
totalarea um^2 --- --- 3251.730 3251.730 3251.730 3251.730 --- 3251.730
utilization % --- --- 39.361 41.453 41.453 41.453 --- 41.453
logicdepth --- --- 0 0 0 0 --- 0
peakpower mw --- --- 0.001 0.001 0.001 0.001 --- 0.001
leakagepower mw --- --- 0.001 0.001 0.001 0.001 --- 0.001
irdrop mv --- --- --- --- --- --- --- 0.005
holdpaths --- --- --- 0 0 0 --- 0
setuppaths --- --- --- 0 0 0 --- 0
macros --- --- 0 0 0 0 --- 0
cells --- 10131 10172 10228 10228 10228 --- 10228
registers --- 1543 1543 1543 1543 1543 --- 1543
buffers --- --- 0 56 56 56 --- 56
inverters --- --- 753 753 753 753 --- 753
pins --- 354 354 354 354 354 --- 354
nets --- 11820 10043 10099 10099 10099 --- 10099
vias --- --- --- --- --- 89867 --- ---
wirelength um --- --- --- --- --- 34939.000 --- ---
memory B 293.230M 224.566M 584.922M 2.061G 610.711M 9.109G 611.008M 932.082M
exetime s 08.890 16.539 15.509 55.659 21.859 01:16.890 05.690 01:25.409
tasktime s 09.702 20.932 16.567 56.806 23.250 01:17.776 07.413 01:26.312
totaltime s 09.702 30.635 47.202 01:44.008 02:07.259 03:25.036 03:32.624 04:51.523
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Metrics for run_benchmark Tasks

Toggle import_verilog0 Metrics
errors warnings drvs drcs unconstrained cellarea totalarea utilization logicdepth peakpower leakagepower irdrop holdpaths setuppaths macros cells registers buffers inverters pins nets vias wirelength memory exetime tasktime totaltime
0 111 --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- 293.230MB 08.890s 09.702s 09.702s
Toggle syn0 Metrics
errors warnings drvs drcs unconstrained cellarea totalarea utilization logicdepth peakpower leakagepower irdrop holdpaths setuppaths macros cells registers buffers inverters pins nets vias wirelength memory exetime tasktime totaltime
0 119 --- --- --- 1305.129um^2 --- --- --- --- --- --- --- --- --- 10131 1543 --- --- 354 11820 --- --- 224.566MB 16.539s 20.932s 30.635s
Toggle floorplan0 Metrics
errors warnings drvs drcs unconstrained cellarea totalarea utilization logicdepth peakpower leakagepower irdrop holdpaths setuppaths macros cells registers buffers inverters pins nets vias wirelength memory exetime tasktime totaltime
0 41 --- --- 1670 1279.920um^2 3251.730um^2 39.361% 0 0.001mw 0.001mw --- --- --- 0 10172 1543 0 753 354 10043 --- --- 584.922MB 15.509s 16.567s 47.202s
Toggle place0 Metrics
errors warnings drvs drcs unconstrained cellarea totalarea utilization logicdepth peakpower leakagepower irdrop holdpaths setuppaths macros cells registers buffers inverters pins nets vias wirelength memory exetime tasktime totaltime
0 42 12 --- 1670 1347.940um^2 3251.730um^2 41.453% 0 0.001mw 0.001mw --- 0 0 0 10228 1543 56 753 354 10099 --- --- 2.061GB 55.659s 56.806s 01:44.008s
Toggle cts0 Metrics
errors warnings drvs drcs unconstrained cellarea totalarea utilization logicdepth peakpower leakagepower irdrop holdpaths setuppaths macros cells registers buffers inverters pins nets vias wirelength memory exetime tasktime totaltime
0 40 12 --- 1670 1347.940um^2 3251.730um^2 41.453% 0 0.001mw 0.001mw --- 0 0 0 10228 1543 56 753 354 10099 --- --- 610.711MB 21.859s 23.250s 02:07.259s
Toggle route0 Metrics
errors warnings drvs drcs unconstrained cellarea totalarea utilization logicdepth peakpower leakagepower irdrop holdpaths setuppaths macros cells registers buffers inverters pins nets vias wirelength memory exetime tasktime totaltime
0 41 128 0 1670 1347.940um^2 3251.730um^2 41.453% 0 0.001mw 0.001mw --- 0 0 0 10228 1543 56 753 354 10099 89867 34939.000um 9.109GB 01:16.890s 01:17.776s 03:25.036s
Toggle write_gds0 Metrics
errors warnings drvs drcs unconstrained cellarea totalarea utilization logicdepth peakpower leakagepower irdrop holdpaths setuppaths macros cells registers buffers inverters pins nets vias wirelength memory exetime tasktime totaltime
0 0 --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- 611.008MB 05.690s 07.413s 03:32.624s
Toggle write_data0 Metrics
errors warnings drvs drcs unconstrained cellarea totalarea utilization logicdepth peakpower leakagepower irdrop holdpaths setuppaths macros cells registers buffers inverters pins nets vias wirelength memory exetime tasktime totaltime
0 40 307 --- 1670 1347.940um^2 3251.730um^2 41.453% 0 0.001mw 0.001mw 0.005mv 0 0 0 10228 1543 56 753 354 10099 --- --- 932.082MB 01:25.409s 01:26.312s 04:51.523s
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